| Aug 25 |
Introduction and Fundamentals (H&P Ch 1) |
Aug 27 |
Technology and Performance (H&P Ch 1, Paper #1) |
| Sep 1 |
Pipelining (H&P Appendix C.1-C.3, Ch 3.1-3.2) |
Sep 3 |
Pipelining: Structural Hazards (H&P Appendix C.1-C.3, Ch 3.1-3.2) |
| Sep 8 |
Pipelining: Data Hazards & Exception Handling (H&P Appendix C.1-C.4, Ch 3.1-3.3, Paper #2) |
Sep 10 |
Pipelining: Control Hazards & Branch Prediction (H&P Ch 3.1-3.3, 3.9) |
| Sep 15 |
Multi-Issue/Superscalar Architectures (H&P Ch 3.7-3.9, Paper #3) |
Sep 17 |
Static ILP (H&P Ch 3, Paper #4) |
| Sep 22 |
Static ILP — Software Pipelineing/Trace Scheduling (H&P Ch 3, Paper #5) |
Sep 24 |
Dynamic ILP – OoO Scoreboard/Tomasulo (H&P Ch 3) |
| Sep 29 |
Dynamic ILP — OoO Tomasulo/ROB/P6 (H&P Ch 3) |
Oct 1 |
Dynamic ILP – OoO P6/R10K/LSQ (H&P Ch 3) |
| Oct 6 |
Caches (H&P Ch 2, Appendix B) |
Oct 8 |
Caches (H&P Ch 2, Appendix B) |
| Oct 13 |
Fall Break – No Class |
Oct 15 |
Midterm (In Class) |
| Oct 20 |
Caches/Virtual Memory (H&P Ch2, Appendix B) |
Oct 22 |
Virtual Memory (H&P Ch 2, Appendix B) |
| Oct 27 |
Multithreading (H&P Ch 3.11) |
Oct 29 |
Thread-Level Parallelism, Multicore/Multiprocessors (H&P Ch 5) |
| Nov 3 |
Shared Memory/Cache Coherence Part I (H&P Ch 5) |
Nov 5 |
Cache Coherence Part II (H&P Ch5) |
| Nov 10 |
Cache Coherence Part III & Memory Consistency (H&P Ch5) |
Nov 12 |
Warehouse Computing (H&P Ch 6) |
| Nov 17 |
Data-Level Parallelism, Vector & GPU Architecture (H&P Ch 4) |
Nov 19 |
Special Topic: TBD |
| Nov 24 |
Special Topic: TBD |
Nov 26 |
Thanksgiving Holiday |
| Dec 1 |
Special Topic: Domain-Specific Accelerators (Papers TBD) |
Dec 3 and Dec 4 |
Final Project Presentations |
