This course is a graduate-level seminar in computer architecture with special topics in hardware acceleration. Advanced undergraduates who have fulfilled the prerequisites are welcome to enroll. This course surveys the landscape of hardware acceleration from historical contexts to recent trends in system designs spanning a collection of architectural techniques (e.g. stream processing, dataflow architecture, parallelism applied to acceleration) and a variety of application domains (e.g. ML, Database, Graph, Robotics, Genomics). This course also covers the taxonomy of accelerators, the hardware-software co-design of accelerators, and the deployment of accelerators using the AWS cloud.
The goal of the course is to provide an essential background in architectural concepts that are applicable to accelerator designs, survey the latest trends in accelerated systems, and introduce an example simple hardware design flow from conceptualizing an accelerator architecture, specifying the accelerator in Chisel, to deploying it on an EC2 F1 instance.
Students are expected to read the assigned papers, provide written reviews/discussion questions for the papers, participate in the paper discussions in class, prepare two lectures on two papers of choice, and complete a course project of a hardware accelerated system (one to two students per project). The success of the project will be measured in a mid-semester proposal checkpoint, end-of-semester poster presentation, a CAL (Computer Architecture Letters)-style written report, and a demo of the accelerator on a Verilog simulator such as VCS or deploying it on the AWS Cloud.
Fall 2019 Mondays and Wednesdays 3:05-4:20pm
Fitzpatrick Schiciano B1466 @ Duke West Campus
Lisa Wu Wills
Office Hour Mondays 4:30-6:00pm @ D304 LSRC or by appointment
Office Hour Tuesdays/Thursdays 3:00-4:00pm @ LSRC B102
Computer Architecture (e.g. CS/ECE 250 or ECE 550) and Digital Logic Design (e.g. CS/ECE 350 or ECE 550) or consent of instructor
CS/ECE 590 Sakai Website is a supplement to the main course website for posting lecture slides, paper/project presentations, lab assignments, Piazza, and your gradebook.
Sign Up Sheets
Chisel Related Resources
Course schedule is tentative and subject to change. Send email to Professor Wills if you have paper suggestions.
Aug 26 · 28
Historical Evolution of Hardware Accelerators
Sep 2 · 4
Sep 9 · 11
Accelerator Taxonomy and Integration
Sep 16 · 18
Accelerated System Performance
Sep 23 · 25
Sep 30 · Oct 2
Parallelism and Efficiency
Project Proposal Checkpoint
Oct 14 · 16
Oct 21 · 23
Domain Specific Accelerators: GPU
Oct 28 · 30
Domain Specific Accelerators: Machine Learning
Nov 4 · 6
Domain Specific Accelerators: Genomic Analytics, Quantum
Nov 11 · 13
Domain Specific Languages and Compilers, Reconfigurable Architectures, Graph Analytics Accelerator
Nov 18 · 20
Domain Specific Accelerators: Robotics, Database Analytics
11.18 Guest Lecture by Professor Dan Sorin on Robotics
Poster Session and Demos