Course Description
This course is a graduate-level seminar in computer architecture with special topics in hardware acceleration. Advanced undergraduates who have fulfilled the prerequisites are welcome to enroll. This course surveys the landscape of hardware acceleration from historical contexts to recent trends in system designs spanning a collection of architectural techniques (e.g. stream processing, dataflow architecture, parallelism applied to acceleration) and a variety of application domains (e.g. ML, Database, Graph, Robotics, Genomics). This course also covers the taxonomy of accelerators, the hardware-software co-design of accelerators, and the deployment of accelerators using the AWS cloud.
The goal of the course is to provide an essential background in architectural concepts that are applicable to accelerator designs, survey the latest trends in accelerated systems, and introduce an example simple hardware design flow from conceptualizing an accelerator architecture, specifying the accelerator in Chisel, to deploying it on an EC2 F1 instance.
Students are expected to read the assigned papers, provide written reviews/discussion questions for the papers, participate in the paper discussions in class, prepare two lectures on two papers of choice, and complete a course project of a hardware accelerated system (one to two students per project). The success of the project will be measured in a mid-semester proposal checkpoint, end-of-semester poster presentation, a CAL (Computer Architecture Letters)-style written report, and a demo of the accelerator on a Verilog simulator such as VCS or deploying it on the AWS Cloud.
When
Fall 2019 Mondays and Wednesdays 3:05-4:20pm
Where
Fitzpatrick Schiciano B1466 @ Duke West Campus
Instructor
Lisa Wu Wills
Office Hour Mondays 4:30-6:00pm @ D304 LSRC or by appointment
Teaching Assistant
Ximing Qiao
Office Hour Tuesdays/Thursdays 3:00-4:00pm @ LSRC B102
Prerequisite
Computer Architecture (e.g. CS/ECE 250 or ECE 550) and Digital Logic Design (e.g. CS/ECE 350 or ECE 550) or consent of instructor
Resources
CS/ECE 590 Sakai Website is a supplement to the main course website for posting lecture slides, paper/project presentations, lab assignments, Piazza, and your gradebook.
A one-day Chisel Bootcamp on September 6 at Teer Building Room 203. This bootcamp is mandatory and will help you in completing the labs. Please register for the bootcamp before it fills up.
Sign Up Sheets
Paper Reading Presentations and Summaries
Chisel Related Resources
Course Syllabus
Course schedule is tentative and subject to change. Send email to Professor Wills if you have paper suggestions.
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Aug 26 · 28
Historical Evolution of Hardware Accelerators
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Sep 2 · 4
Why Accelerators
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Sep 9 · 11
Accelerator Taxonomy and Integration
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Sep 16 · 18
Accelerated System Performance
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Sep 23 · 25
Stream Processing
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Sep 30 · Oct 2
Parallelism and Efficiency
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Oct 9
Project Proposal Checkpoint
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Oct 14 · 16
Dataflow Architecture
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Oct 21 · 23
Domain Specific Accelerators: GPU
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Oct 28 · 30
Domain Specific Accelerators: Machine Learning
● 10.28 DianNao: A Small-Footprint high-throughput accelerator for ubiquitous machine-learning
● 10.28 Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks
● 10.30 In-Datacenter Performance Analysis of a Tensor Processing Unit
● 10.30 Tangram: Optimized Coarse-Grained Dataflow for Scalable NN Accelerators
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Nov 4 · 6
Domain Specific Accelerators: Genomic Analytics, Quantum
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Nov 11 · 13
Domain Specific Languages and Compilers, Reconfigurable Architectures, Graph Analytics Accelerator
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Nov 18 · 20
Domain Specific Accelerators: Robotics, Database Analytics
11.18 Guest Lecture by Professor Dan Sorin on Robotics
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Nov 25
Course Summary
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Dec 4
Poster Session and Demos